1. Field of the Invention
The present invention relates generally to integrated circuit devices (hereinafter referred to as IC devices) and a manufacturing method thereof and, more particularly, to an IC device which can be developed or manufactured at low cost even in case of producing a small number of multi-kind products, and a method of manufacturing such an IC device.
2. Description of the Background Art
With manufacture techniques advanced in recent years, high integration density, high performance of IC devices have been increasingly developed, and hence such IC devices have been playing a more important role in the electronic industry year by year. Moreover, with electronic devices further diversified, there has been a greater demand for IC devices to be produced in small quantities and various types. Conventionally, to produce small quantity custom IC devices of various types, gate array IC devices have been in wide use that employ both a master slice approach manufacture technique and a design technique utilizing CAD (Computer Aided Design). However, in order to further enhance the performance of electronic circuit devices, there have been increasing demands for the IC devices to have higher performance, i.e., higher operation speed, a higher degree of integration, lower power consumption, etc. even on the basis of small quantity production of various types. Such high-performance IC devices on the basis of small quantity production of various types are manufactured with dedicated masks manufactured to be employed in all the manufacturing steps, and also specially configured tools or the like required in these steps are used depending on the specific IC architecture.
The IC devices generally comprise circuits consisting of internal logic circuits and the like, and bonding pads which are terminals for bonding leads for carrying out transmission of electrical signals between the circuits inside the devices and the external device's circuit. A description will now be given on the structure of the IC devices on the basis of small quantity production of various types, that is, an arrangement configuration of circuits and bonding pads with respect to two IC devices having different signal processing functions and different numbers of input/output terminals.
FIGS. 1A and 1B show a conventional example of chip configurations of two IC devices having different signal processing functions and different numbers of input/output terminals. A substrate 10 of a first IC device shown in FIG. 1A and a substrate 20 of a second IC device shown in FIG. 1B are different from each other in size of their main surfaces and in number of and arranged pattern of their respective bonding pads 11, 21. Circuits 12, 22 mainly formed of internal logic circuits are formed in respective regions enclosed by these bonding pads 11, 21 on the respective substrates 10, 20. Input/output terminals of the circuits 12, 22 are subject to an interconnection processing so as to be conductive with their corresponding bonding pads 11, 21.
FIGS. 2A and 2B show a state of wafer test of the first IC device shown in FIG. 1A, focusing on probing of the chip. This wafer test is the step of testing whether or not the chip is satisfactory by checking the operation of the formed circuit at a previous stage of assembling the chip as a finished product after a wafer step is completed. This test is usually carried out at a stage of developing the IC device and in the step of manufacturing the device, before the step of dicing the wafer. During this wafer test, referring to FIGS. 2A and 2B, the tips of probes 31 for probing, extending from a fixed probe card substrate 30, are in contact with the bonding pads 11 on the substrate 10 mounted on a stage 40. Conductive interconnection patterns 32 are formed on a lower surface of the fixed probe card substrate 30, and electrodes 33 for transmitting electric signals to/from a tester (not shown) are formed on a top surface of the fixed probe card substrate 30. The electrodes 33 and interconnection patterns 32 are electrically connected by a conductive substance covering the inner sidewall of through holes 34. The probes 31 are adhered onto the interconnection patterns 32 by a conductive adhesion substance 35.
During the wafer test, referring to FIGS. 2A and 2B, the wafer having a large number of the first IC devices adjacently formed thereon is mounted on the stage 40 to be temporarily secured thereon. The tip of the corresponding probe 31 of the fixed probe card substrate is forced on each bonding pad 11 in a specific chip area on the wafer so as to be electrically connected with the bonding pad 11. Consequently, electrical signals are transmitted between the circuit 12 in the first IC device and the tester through the bonding pad 11, probe 31, adhesion substance 35, interconnection pattern 32, through hole 34 and electrode 33 of the fixed probe card, to perform an operation test of the first IC device.
FIGS. 3A and 3B show a state that the wafer chip is mounted in a package 50 in order to complete the first IC device as a product. Referring to these figures, the substrate 10 is mounted on a surface of the bottom portion 53 in the package 50, and the bonding pad 11 on the substrate 10 is electrically connected to an external lead (not shown) of the package 50 through a bonding wire 51 and an interconnection pattern 52. After the IC substrate 10 is thus incorporated into the package 50, the surface of the substrate and package is covered with a cap so as to form a final product. While the above wafer test and the chip packaging have been described with respect to the first IC device as an example, these steps are carried out for each type of IC device in small quantity custom production runs. That is, the wafer test and the incorporation of the substrate into the package 50 are also carried out for the second IC device, but the relative arrangement of the bonding pads 21 is different from that of the bonding pads 11. Therefore, the position of the tip of the probing probes 31 in contact with the respective bonding pads 2 is adjusted in registration with the arrangement of the bonding pads 21. Also in a case that the substrate 20 is incorporated in the package 50, since the interconnection patterns 52 and bonding pads 21 are connected by the bonding wire 51, the wire bonding of different pattern from that in the case of the above described first IC device is carried out.
The interconnection between one bonding pad 11 and circuit 12 is shown, for example, in FIGS. 4A-4C. A circuit of this IC device is structured as follows, shown in FIG. 4C showing an equivalent circuit thereof. A common terminal 13 for two MOS transistors in the circuit 12 is electrically connected to a lead 11a of the bonding pad 11 through a contact hole 15. The overall surface of the circuit 12 and the surface of the lead 11a of the bonding pad 11 are both covered with an insulator film 16 for protection.
The interconnection between the bonding pad 11 and circuit 12 is sometimes carried out through an input and/or output buffer circuit 17, as shown in FIG. 5. This input and/or output buffer circuit 17 temporarily stores a signal provided from the bonding pad 11 in accordance with the signal processing speed of the circuit 12 so as to allow the processing speed of a circuit outside the device or the like to match with that of the circuit 12.
All the above described bonding pad 11, circuit 12 and input and/or output buffer circuit 17 can undergo extremely miniaturized processes by using conventional photolithography techniques.
The structure of the integrated circuit device on the conventional basis of small quantity production of various types involves the following problems.
In development of the first IC device and second IC device on the conventional basis of small quantity production of various types, when a fixed probe card for the first IC device is employed for the second IC device upon wafer test, since the number of and arranged pattern of the bonding pads 11 and 21 are not identical between the first and second IC devices, electrical connections between the bonding pads 21 and probes 31 are sometimes not achieved. Therefore, it is difficult to use the same fixed probe card in common between the first and second IC devices. Even if the number of bonding pads 11 is almost the same as that of the bonding pads 21, when a package 50 suitable for one of the IC devices is employed for the other IC device to use the same package 50 in common upon incorporating the IC devices into the package 50, it is possible for any adjacent bonding wires 51 to contact each other and cause electrical shorts. Therefore, it is difficult to employ the same package 50 for both IC devices. Thus, developing or manufacturing two types of IC devices requires a dedicated fixed probe card 30 for a dedicated package 50 to be manufactured depending on the type of the IC devices, entailing the problem of an increase in trial manufacturing cost.
In addition, in the wire bonding step for connecting the bonding wire 51, an adjustment in positional accuracy of wire bonding is not easy due to a limitation in mechanical accuracy. Thus, a variation in arranged pattern of the bonding pads 11, 12 requires a great effort for adjusting the positional accuracy of wire bonding, again entailing an increase in manufacturing cost.
The case of developing or manufacturing two types of IC devices has been described in the foregoing example; however, it is considered that there are a very large number of types of IC devices on the common basis of small quantity production of various types, and hence the foregoing problems are very serious in reality.
The foregoing problems can be eliminated by standardizing the size of substrates and the number of and arranged pattern of bonding pads of the IC devices to those of the largest IC device in order to us the fixed probe card 30 and package 50 in common among the plurality of IC devices. However, it causes increased useless regions on the substrates, namely, increased blank spaces between the circuit regions and the bonding pads, resulting in other problems such as a degradation in performance of the IC devices due to an increased resistance with a longer conductive interconnection pattern as well as a degradation in degree of integration of the IC devices.
The above-described wafer test employing the probe card is disclosed in Japanese Patent Laying-Open No. 63-289826. The disclosed probe card is structured such that a large number of probes are arranged and adhered on a first substrate on which a second substrate having a function of selecting only necessary one(s) of outputs from the respective probes is detachably provided. This structure makes it possible to carry out various different wafer tests by only exchanging the second substrate without restration of the probes in each test. However, even if such a probe card is employed, the aforementioned disadvantages have not been eliminated in wafer test on the basis of small quantity production of various types having different arrangements of bonding pads.